Master information

Task description and requirements

• Develop solutions for the verification of the hardware System On Chip (SoC) products;
• Develop, execute and debug a wide range of functional tests in a verilog simulation environment for content processing hardware IP designs;
• Analyze requirements, develop verification plans, test attributes and strategy;
• Develop simulation environment, testcases, drivers, monitors and response checkers;
• Employ constrained random verification approaches when possible;
• Analyze code coverage and address coverage issues;
• Work closely with IC Design Engineers

• 10+ years of experience in constraint random verification, UVM verification and UVM environment development;
• Proficient in test plan definition and testcase development in System Verilog;
• Focus on quality of results, with proven problem-solving abilities;
• Good understanding of coverage analysis, performance verification and use-case verification;
• Fluency with scripting languages (e.g., Makefile, Perl, Python, Shell);
• Ability to effectively communicate verbally and in writing in English and work within all levels of the organization;
• Familiar with Formal and Functional Safety verification

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